The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of fabrication and verification processes for ICs, and, for improvements to be fully realized, similar developments in IC manufacturing are needed.
As merely one example, trench isolation structures, such as shallow-trench isolation structures (STIs), have proven challenging to scale down. Trench isolation structures are dielectric-filled regions sunk into a semiconductor substrate to prevent the flow of current between circuit devices. Electrical isolation generally depends on both the insulation properties of the dielectric material and the amount of dielectric disposed between the circuit devices. Merely shrinking the size of the isolation structure without changing other properties reduces the amount of insulation provided. Compounding the problem, smaller devices are often more sensitive to leakage associated with insufficient isolation. Additionally, current trends towards reduced power means that the operating environments ICs are used in are also becoming increasingly sensitive to leakage. It follows that further advances in trench isolation structures are extremely desirable in order to deliver further improvements in device scaling, power, and other performance metrics. Therefore, while existing fabrication process for forming trench isolation structures have been generally adequate, they have not proved entirely satisfactory in all respects.